The invention concerns a frequency synthesizer which functions according to the principle of fractional frequency synthesis, according to the pre-characterizing clause of the main claim.
Synthesizers of this type are known in the art (e.g. according to published patent specification 196 40 072). In the case of the known synthesizers, the integrator consists of several series-connected integrating circuits, in the feedback loop of which are disposed limiters or evaluation elements. These limiters or evaluation elements are necessary to reduce the control gain to the extent that the closed-loop control circuit is stable. This, however, also reduces the suppression of the quantization noise close to the carrier, this suppression being defined by the gain of the open control loop.
The object of the invention is to create a synthesizer of the initially stated type which has a stable closed-loop control circuit and still has a loop gain which is as high as possible.
This object is achieved by a frequency synthesizer according to the main claim. Advantageous developments are disclosed by the sub-claims.
In the case of the frequency synthesizer according to the invention, the use of known IIR low-pass filters permits both a high loop gain and a stable closed-loop control circuit without increasing the modulation on the frequency divider more than is necessary. Limiting elements in the feedback loop are avoided, the integer component of the correction value being reinjected directly to the input. IIR (Infinite Impulse Response) filters are known in the art and are described more fully in, for example, the book by H. Gxc3x6tz, Einfxc3xcihrung in die digitale Signalverarbeitung (Introduction to Digital Signal Processing), Teubner Studienskripten, page 220. Due to the fine adjustment capability of the multipliers of the IIR filters, it is possible to achieve optimum adjustment of the control characteristic and, consequently, a maximally high loop gain which, in turn, permits optimum suppression of the quantization noise close to the carrier without increasing the modulation on the frequency divider more than is necessary. The small amount of modulation on the frequency divider permits the adjusting of very small division factors, this in turn affording advantages in respect of the phase noise and the adjustment speed. Through optimization of the phase response and attenuation characteristic, the control loop can be designed so that a stable closed-loop control circuit is achieved. The noise profile of the quantization noise can be appropriately adjusted through the selected filter coefficients. The order of the filter is determined by the quantity of registers and multipliers. With a second-order filter, for example, it is possible to achieve a reduction of the quantization noise on the carrier at a rate of approximately 20 dB per decade, and a reduction of 40 dB per decade with a third-order filter, etc. In principle, the order of the filter can be increased as required as long as the rating rules for closed-loop control circuits are observed, i.e., the phase shift in the proximity of the control bandwidth must be less than 180xc2x0.